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Ultralow Noise,200 mA, CMOS Linear Regulator ADP151
FEATURES
Ultralow noise: 9 V rms No noise bypass capacitor required Stable with 1 F ceramic input and output capacitors Maximum output current: 200 mA Input voltage range: 2.2 V to 5.5 V Low quiescent current IGND = 10 A with 0 load IGND = 265 A with 200 mA load Low shutdown current: <1 A Low dropout voltage: 140 mV at 200 mA load Initial accuracy: 1% Accuracy over line, load, and temperature: 2.5% 16 fixed output voltage options: 1.1 V to 3.3 V PSRR performance of 70 dB at 10 kHz Current limit and thermal overload protection Logic controlled enable Internal pull-down resistor on EN input 5-lead TSOT package 4-ball, 0.4mm pitch WLCSP
TYPICAL APPLICATION CIRCUIT
VIN = 2.3V 1F
2 1
VIN GND EN
VOUT 5
VOUT = 1.8V 1F
ON OFF
3
NC 4
08627-001
NC = NO CONNECT
Figure 1. TSOT ADP151 with Fixed Output Voltage, 1.8 V
1 VIN = 2.3V CIN TOP VIEW (Not to Scale) ON OFF EN GND B VIN 2 VOUT = 1.8V VOUT A COUT 1F
08627-002
Figure 2. WLCSP ADP151 with Fixed Output Voltage, 1.8 V
APPLICATIONS
RF, VCO, and PLL power supplies Mobile phones Digital camera and audio devices Portable and battery-powered equipment Post dc-to-dc regulation Portable medical devices
GENERAL DESCRIPTION
The ADP151 is an ultralow noise, low dropout, linear regulator that operates from 2.2 V to 5.5 V and provides up to 200 mA of output current. The low 140 mV dropout voltage at 200 mA load improves efficiency and allows operation over a wide input voltage range. Using an innovative circuit topology, the ADP151 achieves ultralow noise performance without the necessity of a bypass capacitor, making it ideal for noise-sensitive analog and RF applications. The ADP151 also achieves ultralow noise performance without compromising PSRR or transient line and load performance. The low 265 A of quiescent current at 200 mA load makes the ADP151 suitable for battery-operated portable equipment. The ADP151 also includes an internal pull-down resistor on the EN input. The ADP151 is specifically designed for stable operation with tiny 1 F, 30% ceramic input and output capacitors to meet the requirements of high performance, space constrained applications. The ADP151 is capable of 16 fixed output voltage options, ranging from 1.1 V to 3.3 V. Short-circuit and thermal overload protection circuits prevent damage in adverse conditions. The ADP151 is available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch, halide-free WLCSP packages for the smallest footprint solution to meet a variety of portable power application requirements.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
ADP151 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Input and Output Capacitor, Recommended Specifications .. 4 Absolute Maximum Ratings ............................................................ 5 Thermal Data ................................................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 11 Applications Information .............................................................. 12 Capacitor Selection .................................................................... 12 Enable Feature ............................................................................ 13 Adjustable Output Voltage Operation ..................................... 13 Current Limit and Thermal Overload Protection ................. 15 Thermal Considerations............................................................ 15 Printed Circuit Board Layout Considerations ............................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 21
REVISION HISTORY
3/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADP151 SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater; EN= VIN, IOUT = 10 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted. Table 1.
Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND Conditions TJ = -40C to +125C IOUT = 0 A IOUT = 0 A, TJ = -40C to +125C IOUT = 100 A IOUT = 100 A, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C EN = GND EN = GND, TJ = -40C to +125C IOUT = 10 mA TJ = -40C to +125C VOUT < 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V VOUT 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V TJ = -40C to +125C VOUT < 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V VOUT 1.8 V 100 A < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V VIN = (VOUT + 0.4 V) to 5.5 V, TJ = -40C to +125C VOUT < 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C VOUT 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C VOUT < 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C VOUT 1.8 V IOUT = 100 A to 200 mA IOUT = 100 A to 200 mA, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C Min 2.2 Typ 10 20 20 40 60 90 265 350 0.2 1.0 -1 +1 Max 5.5 Unit V A A A A A A A A A A %
SHUTDOWN CURRENT OUTPUT VOLTAGE ACCURACY TSOT
IGND-SD
VOUT VOUT
-3 -2.5
+2 +1.5
% %
WLCSP
VOUT
-2.5 -2 -0.05 0.006
+2 +1.5 +0.05
% % %/V %/mA %/mA %/mA %/mA %/mA %/mA %/mA %/mA %/mA %/mA mV mV mV mV mV mV
REGULATION Line Regulation Load Regulation (TSOT)1
VOUT/VIN VOUT/IOUT
0.012 0.003 0.008 0.004 0.009 0.002 0.006 10 30 150 230 135 200
Load Regulation (WLCSP)1
VOUT/IOUT
DROPOUT VOLTAGE2 TSOT WLCSP
VDROPOUT
Rev. 0 | Page 3 of 24
ADP151
Parameter START-UP TIME3 CURRENT LIMIT THRESHOLD4 UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling Hysteresis THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Pull-Down Resistance OUTPUT NOISE Symbol TSTART-UP ILIMIT UVLORISE UVLOFALL UVLOHYS TSSD TSSD-HYS VIH VIL REN OUTNOISE TJ rising Conditions VOUT = 3.3 V TJ = -40C to +125C TJ = -40C to +125C Min 220 Typ 180 300 Max 400 1.96 1.28 120 150 15 1.2 0.4 2.6 9 9 9 70 55 70 55 70 55 Unit s mA V V mV C C V V M V rms V rms V rms dB dB dB dB dB dB
2.2 V VIN 5.5 V 2.2 V VIN 5.5 V VIN = VEN = 5.5 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.1 V 10 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 10 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 100 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 10 kHz, VIN = 2.2 V, VOUT = 1.1 V, IOUT = 10 mA 100 kHz, VIN = 2.2 V, VOUT = 1.1 V, IOUT = 10 mA
POWER SUPPLY REJECTION RATIO VIN = VOUT + 0.5 V VIN = VOUT + 1 V
PSRR
Based on an end-point calculation using 0.1 mA and 200 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.2 V. 3 Start-up time is defined as the time between the rising edge of EN and VOUT being at 90% of its nominal value. 4 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V (that is, 2.7 V).
1 2
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Parameter Minimum Input and Output Capacitance1 Capacitor ESR
1
Symbol CMIN RESR
Conditions TA = -40C to +125C TA = -40C to +125C
Min 0.7 0.001
Typ
Max
Unit F
0.2
The minimum input and output capacitance should be greater than 0.7 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 24
ADP151 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VIN to GND VOUT to GND EN to GND Storage Temperature Range Operating Junction Temperature Range Operating Ambient Temperature Range Soldering Conditions Rating -0.3 V to +6.5 V -0.3 V to VIN -0.3 V to +6.5V -65C to +150C -40C to +125C -40C to +125C JEDEC J-STD-020
specified values of JA are based on a 4-layer, 4 in. x 3 in. circuit board. See JESD51-7 and JESD51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package, available at www.analog.com. JB is the junction-to-board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) See JESD51-8 and JESD51-12 for more detailed information about JB.
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in combination. The ADP151 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD x JA) Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of J may vary, depending on A PCB material, layout, and environmental conditions. The
THERMAL RESISTANCE
JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 5-Lead TSOT 4-Ball, 0.4 mm Pitch WLCSP JA 170 260 JB 43 58 Unit C/W C/W
ESD CAUTION
Rev. 0 | Page 5 of 24
ADP151 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
VIN 1
5
2 VOUT
VOUT
ADP151
GND 2 EN 3 TOP VIEW (Not to Scale)
08627-003
A
VIN
TOP VIEW (Not to Scale) B EN GND
08627-004
4
NC
NC = NO CONNECT
Figure 3. 5-Lead TSOT Pin Configuration
Figure 4. 4-Ball WLCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. TSOT WLCSP 1 A1 2 B2 3 B1 4 5 N/A A2 Mnemonic VIN GND EN NC VOUT Description Regulator Input Supply. Bypass VIN to GND with a 1 F or greater capacitor. Ground. Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. No Connect. Not connected internally. Regulated Output Voltage. Bypass VOUT to GND with a 1 F or greater capacitor.
Rev. 0 | Page 6 of 24
ADP151 TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted.
3.35 300
3.33
GROUND CURRENT (A)
200
VOUT (V)
3.31
3.29 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA
08627-005
100 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA -40 -5 25 85 125
08627-008
3.27
3.25
0
-40
-5
25
85
125
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 5. Output Voltage vs. Junction Temperature
3.35 1k
Figure 8. Ground Current vs. Junction Temperature
3.33
VOUT (V)
3.31
GROUND CURRENT (A)
100
3.29
3.27
0.1
1
10 ILOAD (mA)
100
1000
0.1
1
10 ILOAD (mA)
100
1000
Figure 6. Output Voltage vs. Load Current
3.35 1k
Figure 9. Ground Current vs. Load Current
LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA
3.33
VOUT (V)
3.31
GROUND CURRENT (A)
100
3.29 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA
08627-007
3.27
3.8
4.0
4.2
4.4
4.6 VIN (V)
4.8
5.0
5.2
5.4
3.8
4.0
4.2
4.4
4.6 VIN (V)
4.8
5.0
5.2
5.4
Figure 7. Output Voltage vs. Input Voltage
Figure 10. Ground Current vs. Input Voltage
Rev. 0 | Page 7 of 24
08627-010
3.25 3.6
10 3.6
08627-009
08627-006
3.25 0.01
10 0.01
ADP151
0.45 0.40
SHUTDOWN CURRENT (A)
0.35 0.30 0.25 0.20 0.15 0.10 0.05
GROUND CURRENT (A)
VIN = 3.6V VIN = 3.8V VIN = 4.2V VIN = 4.4V VIN = 4.8V VIN = 5.5V
800 700 600 500 400 300 200 100 0 3.10
IOUT = 1mA IOUT = 5mA IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 200mA
08627-011
-25
0
25
50
75
100
125
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
TEMPERATURE (C)
VIN (V)
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
120
Figure 14. Ground Current vs. Input Voltage (in Dropout)
0 -10 200mA 100mA 10mA 1mA 100A
100
-20
80
PSRR (dB)
-30 -40 -50 -60 -70
DROPOUT (mA)
60
40
20
-80 -90
1 10 ILOAD (mA) 100 1000
08627-015 08627-016
08627-012
0
-100 10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 12. Dropout Voltage vs. Load Current
3.40 3.35 3.30
Figure 15. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.2 V
0 -10 -20 -30
PSRR (dB)
200mA 100mA 10mA 1mA 100A
3.25
VOUT (V)
-40 -50 -60 -70 -80 -90
3.20 3.15 3.10 3.05 3.00 3.10 IOUT = 1mA IOUT = 5mA IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 200mA 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55
08627-013
-100 10
100
1k
10k
100k
1M
10M
VIN (V)
FREQUENCY (Hz)
Figure 13. Output Voltage vs. Input Voltage (in Dropout)
Figure 16. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.8 V
Rev. 0 | Page 8 of 24
08627-014
0 -50
ADP151
0 -10 -20 -30
PSRR (dB)
200mA 100mA 10mA 1mA 100A
NOISE (V rms)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
08627-017
3.3V 2.8V 1.2V 1.1V
-40 -50 -60 -70 -80 -90 -100 10
100
1k
10k
100k
1M
10M
0.01
0.1
1
10
100
1k
FREQUENCY (Hz)
LOAD CURRENT (mA)
Figure 17. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V
0 -10 -20 -30
PSRR (dB)
Figure 20. Output Noise vs. Load Current and Output Voltage, VIN = 5 V, COUT = 1 F
1 3.3V 2.8V 1.2V 1.1V
VOUT = 3.3V, VOUT = 3.3V, VOUT = 2.8V, VOUT = 2.8V, VOUT = 1.1V, VOUT = 1.1V,
IOUT = 200mA IOUT = 10mA IOUT = 200mA IOUT = 10mA IOUT = 200mA IOUT = 10mA
(nV/ Hz)
-40 -50 -60 -70 -80 -90
08627-018
0.1
100
1k
10k
100k
1M
10M
100
1k FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency at Various Output Voltages and Load Currents
0 -10 -20 -30
PSRR (dB)
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 F
IOUT IOUT IOUT IOUT
= 200mA, VIN = 3.3V = 10mA, VIN =3.3V = 200mA, VIN = 3.8V = 10mA, VIN = 3.8V
T
LOAD CURRENT
1
-40 -50 -60 -70 -80 -90
08627-019
2
VOUT
-100 10
100
1k
10k
100k
1M
10M
CH1 200mA
CH2 50mV
FREQUENCY (Hz)
M20s T 10.00%
A CH1
64.0mA
Figure 19. Power Supply Rejection Ratio vs. Frequency at Various Voltages and Load Currents, VOUT = 2.8 V
Figure 22. Load Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA to 200 mA
Rev. 0 | Page 9 of 24
08627-022
08627-021
-100 10
0.01 10
08627-020
0 0.001
ADP151
T T
INPUT VOLTAGE
INPUT VOLTAGE
2
2
VOUT
1 1
VOUT
08627-023
CH1 1V
CH2 2mV
M10s T 10.80%
A CH1
4.56V
CH1 1V
CH2 2mV
M10s T 10.80%
A CH1
4.56V
Figure 23. Line Transient Response, CIN, COUT = 1 F, ILOAD = 200 mA
Figure 24. Line Transient Response, CIN, COUT =1 F, ILOAD = 1 mA
Rev. 0 | Page 10 of 24
08627-024
ADP151 THEORY OF OPERATION
The ADP151 is an ultralow noise, low quiescent current, low dropout linear regulator that operates from 2.2 V to 5.5 V and can provide up to 200 mA of output current. Drawing a low 265 A of quiescent current (typical) at full load makes the ADP151 ideal for battery-operated portable equipment. Shutdown current consumption is typically 200 nA. Using new innovative design techniques, the ADP151 provides superior noise performance for noise-sensitive analog and RF applications without the need for a noise bypass capacitor. The ADP151 is also optimized for use with small 1 F ceramic capacitors.
VIN VOUT
Internally, the ADP151 consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. An internal pull-down resistor on the EN input holds the input low when the pin is left open. The ADP151 is available in 16 output voltage options, ranging from 1.1 V to 3.3 V. The ADP151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on; when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN.
R1 GND SHORT CIRCUIT, UVLO, AND THERMAL PROTECT
EN REN
SHUTDOWN REFERENCE
R2
08627-025
Figure 25. Internal Block Diagram
Rev. 0 | Page 11 of 24
ADP151 APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP151 is designed for operation with small, space-saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 1 F capacitance with an ESR of 1 or less is recommended to ensure the stability of the ADP151. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP151 to large changes in load current. Figure 26 shows the transient responses for an output capacitance value of 1 F.
T
Figure 27 depicts the capacitance vs. voltage bias characteristic of an 0402, 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~15% over the -40C to +85C temperature range and is not a function of package or voltage rating.
1.2
1.0
CAPACITANCE (F)
0.8
0.6
LOAD CURRENT
0.4
1
0.2
0
2
2
4 VOLTAGE
6
8
10
Figure 27. Capacitance vs. Voltage Characteristic
VOUT
Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage.
08627-026
CH1 200mA
CH2 50mV
M20s T 10.00%
A CH1
64mA
CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance.
08627-027
0
(1)
Figure 26. Output Transient Response, COUT = 1 F
Input Bypass Capacitor
Connecting a 1 F capacitor from VIN to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If greater than 1 F of output capacitance is required, the input capacitor should be increased to match it.
In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V as shown in Figure 27. , Substituting these values in Equation 1 yields CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP151, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the ADP151, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics.
Rev. 0 | Page 12 of 24
ADP151
ENABLE FEATURE
The ADP151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 28, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off.
3.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.0 0 1.5 0 50 100 150 200 250 300 350 TIME (s) 1.0 ENABLE 3.3V 2.8V 1.1V 400 450
08627-030
2.5
VOUT
ENABLE VOLTAGE
Figure 30. Typical Start-Up Behavior
ADJUSTABLE OUTPUT VOLTAGE OPERATION
0.5 0 0 0.5 1.0 1.5 2.0 2.5 ENABLE VOLTAGE
The unique architecture of the ADP151 makes an adjustable version difficult to implement in silicon. However, it is possible to create an adjustable regulator at the expense of increasing the quiescent current of the regulator circuit. The ADP151, and similar LDOs, are designed to regulate the output voltage, VOUT, appearing at the VOUT pin with respect to the GND pin. If the GND pin is at a potential other than 0 V (for example, at VOFFSET), the ADP151 output voltage is VOUT + VOFFSET. By taking advantage of this behavior, it is possible to create an adjustable ADP151 circuit that retains most of the desirable characteristics of the ADP151.
VIN C1
2 1
Figure 28. ADP151 Typical EN Pin Operation
As shown in Figure 28, the EN pin has hysteresis built in. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active/inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 29 shows typical EN active/inactive thresholds when the input voltage varies from 2.2 V to 5.5 V.
1200
08627-028
VIN GND EN
VOUT 5
VOUT C2
U1
1000 VEN RISE VEN FALL 600
VOFFSET R2
3
NC 4
ENABLE VOLTAGE
C3 VOUT = VLDO x (1 + R1/R2)
Figure 31. Adjustable LDO Using the ADP151
400
200
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE
08627-029
0 2.0
The circuit shown in Figure 31 is an example of an adjustable LDO using the ADP151. A stable VOFFSET voltage is created by passing a known current through R2. The current through R2 is determined by the voltage across R1. Because the voltage across R1 is set by the voltage between VOUT and GND, the current passing through R2 is fixed, and VOFFSET is stable. To minimize the effect variation of the ADP151 ground current, IGND, with load, it is best to keep R1 as small as possible. It is also best to size the current passing through R2 to at least 20x greater than the maximum expected ground current. To create a 4 V LDO circuit, start with the 3.3 V version of the ADP151 to minimize the value of R2. Because VOUT is 4 V, VOFFSET must be 0.7 V, and the current through R2 must be 7 mA. R1 is, therefore, 3.3 V/7 mA or 471 . A 470 standard value introduces less than 1% error. Capacitor C3 is necessary to stabilize the LDO; a value of 1 F is adequate.
Figure 29. Typical EN Pin Thresholds vs. Input Voltage
The ADP151 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 3.3 V option is approximately 160 s from the time the EN active threshold is crossed to when the output reaches 90% of its final value. As shown in Figure 30, the start-up time is dependent on the output voltage setting.
Rev. 0 | Page 13 of 24
08627-131
800
R1
ADP151
Figure 32 through Figure 36 show the typical performance of the 4 V LDO circuit. The noise performance of the 4 V LDO circuit is only about 1 V worse than the same LDO used at 3.3 V because the output noise of the circuit is almost solely determined by the LDO and not the external components. The small difference may be attributed to the internally generated noise in the LDO ground current working with R2. By keeping R2 small, this noise contribution can be minimized. The PSRR of the 4 V circuit is as much as 10 dB poorer than the 3.3. V LDO with 500 mV of headroom because the ground current of the LDO varies somewhat with input voltage. This, in turn, modulates VOFFSET and reduces the PSRR of the regulator. By increasing the headroom to 1 V, the PSRR performance is nearly restored to the performance of the fixed output LDO.
4.04 4.03
1
11
NOISE (V rms)
10
9
1
10
100
1k
LOAD CURRENT (mA)
Figure 34. 4 V Load Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz
T
4.02 4.01
VOUT (V)
4.00
2
3.99 3.98 3.97 3.96 LOAD = 10mA LOAD = 20mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA -40 -5 25 85 125
08627-132
CH1 100mA
CH2 50mV
M40s T 10.20%
A CH1
52.0mA
JUNCTION TEMPERATURE (C)
Figure 35. 4 V Load Circuit, Typical PSRR vs. Load Current, 1 V Headroom
T
Figure 32. 4 V LDO Circuit, Typical Load Regulation over Temperature
4.040 4.035 4.030 4.025 LOAD = 10mA LOAD = 20mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA
1
VOUT (V)
4.020 4.015 4.010 4.005
2
CH1 100mA
CH2 50mV
4.6
4.8
5.0 VIN (V)
5.2
5.4
08627-133
4.000 4.4
M40s T 10.20%
A CH1
52.0mA
Figure 36. 4 V Load Circuit, Typical PSRR vs. Load Current, 500 mV Headroom
Figure 33. 4 V LDO Circuit, Typical Line Regulation over Load Current
Rev. 0 | Page 14 of 24
08627-136
08627-135
08627-134
8
ADP151
CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION
The ADP151 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP151 is designed to current limit when the output load reaches 300 mA (typical). When the output load exceeds 300 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150C, the output is turned off, reducing the output current to 0. When the junction temperature drops below 135C, the output is turned on again, and output current is restored to its nominal value. Consider the case where a hard short from VOUT to ground occurs. At first, the ADP151 current limits, so that only 300 mA is conducted into the short. If self-heating of the junction is great enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to 0. As the junction temperature cools and drops below 135C, the output turns on and conducts 300 mA into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between 300 mA and 0 mA that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125C. changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB. Table 5 shows typical JA values of the 5-lead TSOT package for various PCB copper sizes. Table 6 shows the typical JB values of the 5-lead TSOT and 4-ball WLCSP. Table 5. Typical JA Values
Copper Size (mm2) 01 50 100 300 500
1
TSOT 170 152 146 134 131
JA (C/W) WLCSP 260 159 157 153 151
Device soldered to minimum size pin traces.
Table 6. Typical JB Values
Model TSOT WLCSP JB (C/W) 43 58
The junction temperature of the ADP151 can be calculated from the following equation: TJ = TA + (PD x JA) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125C. Figure 37 to Figure 50 show junction temperature calculations for different ambient temperatures, load currents, VIN-to-VOUT differentials, and areas of PCB copper. (3) (2)
THERMAL CONSIDERATIONS
In most applications, the ADP151 does not dissipate much heat due to its high efficiency. However, in applications with high ambient temperature, high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125C. When the junction temperature exceeds 150C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 135C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADP151 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature
Rev. 0 | Page 15 of 24
ADP151
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3 140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3
JUNCTION TEMPERATURE, TJ (C)
JUNCTION TEMPERATURE, TJ (C)
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
08627-031
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
08627-034 08627-036 08627-035
2.3 2.8 3.3 VIN - VOUT (V)
2.3 2.8 3.3 VIN - VOUT (V)
Figure 37. WLCSP 500 mm2 of PCB Copper, TA = 25C
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3 140
Figure 40. WLCSP 500 mm2 of PCB Copper, TA = 50C
MAXIMUM JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C)
JUNCTION TEMPERATURE, TJ (C)
120 100 80 60 40 20 0 0.3
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
08627-032
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
2.3 2.8 3.3 VIN - VOUT (V)
2.3 2.8 3.3 VIN - VOUT (V)
Figure 38. WLCSP 100 mm2 of PCB Copper, TA = 25C
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3 140
Figure 41. WLCSP 100 mm2 of PCB Copper, TA = 50C
MAXIMUM JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C)
JUNCTION TEMPERATURE, TJ (C)
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
120 100 80 60 40 20 0 0.3
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
08627-033
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
2.3 2.8 3.3 VIN - VOUT (V)
2.3 2.8 3.3 VIN - VOUT (V)
Figure 39. WLCSP 50 mm2 of PCB Copper, TA = 25C
Figure 42. WLCSP 50 mm2 of PCB Copper, TA = 50C
Rev. 0 | Page 16 of 24
ADP151
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3 140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3
JUNCTION TEMPERATURE, TJ (C)
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA
08627-037
JUNCTION TEMPERATURE, TJ (C)
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
08627-040 08627-042 08627-041
2.3 2.8 3.3 VIN - VOUT (V)
3.8
4.3
4.8
2.3 2.8 3.3 VIN - VOUT (V)
Figure 43. TSOT 500 mm2 of PCB Copper, TA = 25C
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3 140
Figure 46. TSOT 500 mm2 of PCB Copper, TA = 50C
MAXIMUM JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C)
JUNCTION TEMPERATURE, TJ (C)
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
120 100 80 60 40 20 0 0.3
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA
08627-038
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
2.3 2.8 3.3 VIN - VOUT (V)
3.8
4.3
4.8
2.3 2.8 3.3 VIN - VOUT (V)
Figure 44. TSOT 100 mm2 of PCB Copper, TA = 25C
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3 140
Figure 47. TSOT 100 mm2 of PCB Copper, TA = 50C
MAXIMUM JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C)
JUNCTION TEMPERATURE, TJ (C)
120 100 80 60 40 20 0 0.3
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA
08627-039
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
2.3 2.8 3.3 VIN - VOUT (V)
3.8
4.3
4.8
2.3 2.8 3.3 VIN - VOUT (V)
Figure 45. TSOT 50 mm2 of PCB Copper, TA = 25C
Figure 48. TSOT 50 mm2 of PCB Copper, TA = 50C
Rev. 0 | Page 17 of 24
ADP151
JUNCTION TEMPERATURE, TJ (C)
In the case where the board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise (see Figure 49 and Figure 50). Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: TJ = TB + (PD x JB) (5) The typical value of is 58C/W for the 4-ball WLCSP package JB and 43C/W for the 5-lead TSOT package.
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3
140 MAXIMUM JUNCTION TEMPERATURE 120 100 80 60 40 20 0 0.3
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
08627-044
JUNCTION TEMPERATURE, TJ (C)
2.3 2.8 3.3 VIN - VOUT (V)
Figure 50. TSOT, TA = 85C
ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA 0.8 1.3 1.8
ILOAD = 100mA ILOAD = 150mA ILOAD = 200mA 3.8 4.3 4.8
08627-043
2.3 2.8 3.3 VIN - VOUT (V)
Figure 49. WLCSP, TA = 85C
Rev. 0 | Page 18 of 24
ADP151 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP151. However, as listed in Table 5, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited.
Figure 52. Example WLCSP PCB Layout
Figure 51. Example TSOT PCB Layout
Rev. 0 | Page 19 of 24
08627-045
08627-046
ADP151 OUTLINE DIMENSIONS
2.90 BSC
5 4
1.60 BSC
1 2 3
2.80 BSC
0.95 BSC *0.90 MAX 0.70 MIN 1.90 BSC
*1.00 MAX
0.20 0.08 8 4 0 0.60 0.45 0.30
100708-A
0.10 MAX
0.50 0.30
SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 53. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions show in millimeters
0.660 0.600 0.540 SEATING PLANE 0.280 0.260 0.240 0.40 BALL PITCH TOP VIEW
(BALL SIDE DOWN)
0.800 0.760 SQ 0.720
0.430 0.400 0.370
2
1 A
BALL A1 IDENTIFIER
B
Figure 54. 4-Ball Wafer Level Chip Scale Package [WLCSP] (CB-4-3) Dimensions show in millimeters
Rev. 0 | Page 20 of 24
011509-A
0.230 0.200 0.170
BOTTOM VIEW
(BALL SIDE UP)
0.050 NOM COPLANARITY
ADP151
ORDERING GUIDE
Model1 ADP151ACBZ-1.2-R7 ADP151ACBZ-1.5-R7 ADP151ACBZ-1.8-R7 ADP151ACBZ-2.5-R7 ADP151ACBZ-2.75-R7 ADP151ACBZ-2.8-R7 ADP151ACBZ-2.85-R7 ADP151ACBZ-3.0-R7 ADP151ACBZ-3.3-R7 ADP151ACBZ-2.1-R7 ADP151AUJZ-1.2-R7 ADP151AUJZ-1.5-R7 ADP151AUJZ-1.8-R7 ADP151AUJZ-2.5-R7 ADP151AUJZ-2.8-R7 ADP151AUJZ-3.0-R7 ADP151AUJZ-3.3-R7
1 2
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Output Voltage (V) 2 1.2 1.5 1.8 2.5 2.75 2.8 2.85 3.0 3.3 2.1 1.2 1.5 1.8 2.5 2.8 3.0 3.3
Package Description 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT
Package Option CB-4-33 CB-4-33 CB-4-33 CB-4-33 CB-4-33 CB-4-33 CB-4-33 CB-4-33 CB-4-33 CB-4-33 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5
Branding 4R 4S 4T 4U 4V 4X 4Y 4Z 50 5E LF6 LF7 LF8 LF9 LFG LFH LFJ
Z = RoHS Compliant Part. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. 3 This package option is halide free.
Rev. 0 | Page 21 of 24
ADP151 NOTES
Rev. 0 | Page 22 of 24
ADP151 NOTES
Rev. 0 | Page 23 of 24
ADP151 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08627-0-3/10
Rev. 0 | Page 24 of 24

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